System and method of VLIW instruction processing using reduced-width VLIW processor
US11663011B2 · kind B2 · utility
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12References
20Claims
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Key dates
| Filing date | Jul 7, 2020 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Jul 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.