Christopher Edward Koob
37Patents
4h-index
48Co-inventors
63Inventor score
Filing activity: Oct 2, 1998 → Oct 22, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6252600A | Computer graphics system with dual FIFO interface | Physics | 32 | Expired |
| US8341353B2 | System and method to access a portion of a level two memory and a level one memory | Physics | 14 | Active |
| US9606818B2 | Systems and methods of executing multiple hypervisors using multiple sets of processors | Physics | 4 | Active |
| US10169246B2 | Reducing metadata size in compressed memory systems of processor-based systems | Physics | 4 | Active |
| US7313089B2 | Method and apparatus for switching between active and standby switch fabrics with no loss of data | Electricity | 3 | Expired |
| US8719503B2 | Configurable cache and method to configure same | Physics | 3 | Active |
| US10198362B2 | Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems | Physics | 3 | Active |
| US6801991B2 | Method and apparatus for buffer partitioning without loss of data | Physics | 3 | Expired |
| US9239799B2 | Memory management unit directed access to system interfaces | Emerging Cross-Sectional Technologies | 3 | Active |
| US10114756B2 | Externally programmable memory management unit | Physics | 3 | Active |
| US7584233B2 | System and method of counting leading zeros and counting leading ones in a digital signal processor | Physics | 3 | Active |
| US10025711B2 | Hybrid write-through/write-back cache policy managers, and related systems and methods | Emerging Cross-Sectional Technologies | 2 | Active |
| US6668313B2 | Memory system for increased bandwidth | Physics | 2 | Expired |
| US9785211B2 | Independent power collapse methodology | Emerging Cross-Sectional Technologies | 2 | Active |
| US7111289B2 | Method for implementing dual link list structure to enable fast link-list pointer updates | Physics | 2 | Expired |
| US8266409B2 | Configurable cache and method to configure same | Physics | 2 | Active |
| US8995207B2 | Data storage for voltage domain crossings | Physics | 1 | Active |
| US7797366B2 | Power-efficient sign extension for booth multiplication methods and systems | Physics | 1 | Active |
| US9678758B2 | Coprocessor for out-of-order loads | Physics | 1 | Active |
| US9501332B2 | System and method to reset a lock indication | Emerging Cross-Sectional Technologies | 1 | Active |
| US7809783B2 | Booth multiplier with enhanced reduction tree circuitry | Physics | 1 | Active |
| US8656137B2 | Computer system with processor local coherency for virtualized input/output | Emerging Cross-Sectional Technologies | 1 | Active |
| US10102031B2 | Bandwidth/resource management for multithreaded processors | Physics | 0 | Active |
| US11663011B2 | System and method of VLIW instruction processing using reduced-width VLIW processor | Physics | 0 | Active |
| US9658793B2 | Adaptive mode translation lookaside buffer search and access fault | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.