Heterogenous-latency memory optimization
US11663138B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2021 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Dec 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.