Method to repair edge placement errors in a semiconductor device
US11664274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2019 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Sep 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include edge placement error mitigation processes and structures fabricated with such processes. In an embodiment, a method of fabricating an interconnect layer over a semiconductor die comprises forming a patterned layer over a substrate, disposing a resist layer over the patterned layer and patterning the resist layer to expose portions of the patterned layer. In an embodiment, overlay misalignment during the patterning results in the formation of edge placement error openings. In an embodiment, the method further comprises correcting the edge placement error openings, and patterning an opening into the substrate after correcting edge placement error openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.