Inventor · Hillsboro, OR, US

Mohit K. HARAN

25Patents
2h-index
63Co-inventors
52Inventor score

Filing activity: Dec 22, 2015 → Feb 9, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US10319625B2 Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures Electricity 4 Active
US11145541B2 Conductive via and metal line end fabrication and structures resulting therefrom Electricity 3 Active
US11393754B2 Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication Electricity 2 Active
US11664274B2 Method to repair edge placement errors in a semiconductor device Electricity 1 Active
US11972979B2 1D vertical edge blocking (VEB) via and plug Electricity 0 Active
US11990472B2 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Electricity 0 Active
US12261122B2 Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication Electricity 0 Active
US12369392B2 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Electricity 0 Active
US11171043B2 Plug and trench architectures for integrated circuits and methods of manufacture Electricity 0 Active
US11652045B2 Via contact patterning method to increase edge placement error margin Electricity 0 Active
US10636700B2 Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures Electricity 0 Active
US12419085B2 Integrated circuit structures having backside gate tie-down Electricity 0 Active
US12308284B2 Plug and trench architectures for integrated circuits and methods of manufacture Electricity 0 Active
US12199161B2 Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication Electricity 0 Active
US12237223B2 Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication Electricity 0 Active
US12310060B2 Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances Electricity 0 Active
US12382721B2 Integrated circuit structures having cut metal gates with dielectric spacer fill Electricity 0 Active
US12237388B2 Transistor arrangements with stacked trench contacts and gate straps Electricity 0 Active
US12400913B2 Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication Electricity 0 Active
US11211324B2 Via contact patterning method to increase edge placement error margin Electricity 0 Active
US12002678B2 Gate spacing in integrated circuit structures Performing Operations; Transporting 0 Active
US11721580B2 1D vertical edge blocking (VEB) via and plug Electricity 0 Active
US12080639B2 Contact over active gate structures with metal oxide layers to inhibit shorting Electricity 0 Active
US12154855B2 Self-aligned patterning with colored blocking and structures resulting therefrom Electricity 0 Active
US12406931B2 Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.