Nonvolatile memory device for increasing reliability of data detected through page buffer
US11670378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Dec 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.