Memory system capable of reducing the reading time
US11670384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2022 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Jan 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bias circuit, a memory system, and a method of boosting a voltage level of a first bit line are provided. The bias circuit includes a first current generator, a second current generator, and a bit line bias generator. The first current generator is configured to generate a first replica charging current according to a charging current flowing through a voltage bias transistor. The second current generator is configured to generate a first replica cell current according to a cell current flowing through a common source transistor. The bit line bias generator is coupled to a first page buffer, the first current generator, and the second current generator, and configured to generate a bit line bias voltage, supplied to the first page buffer, according to a comparison of the first replica charging current and the first replica cell current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.