Method for forming lead wires in hybrid-bonded semiconductor devices
US11670543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2022 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Mar 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of methods for forming a hybrid-bonded semiconductor structure are disclosed. The method include disposing first second, third, and fourth dielectric layers, forming first and second openings by etching the fourth dielectric layer using a first etching selectivity, etching the third and fourth dielectric layers in the first and second openings respectively using a second etching selectivity, etching the second and third dielectric layers in the first and second openings using the first etching selectivity, etching the first dielectric layer in the first opening and the second dielectric layer in the second opening using the second etching selectivity, etching the first dielectric layer in the first and second openings using the first etching selectivity, and forming conductive material in the first and second openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.