Gate stack treatment
US11670553B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 9, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Aug 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.