Memory-type camouflaged logic gate using transistors with different threshold voltages
US11671101B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Sep 8, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Sep 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.