Offset calibration for successive approximation register analog to digital converter
US11671108B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2022 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Apr 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.