Methods and apparatus for reducing switching time of RF FET switching devices
US11671135B2 · kind B2 · utility
5Cited by
17References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.