Methods and apparatus for profile-guided optimization of integrated circuits
US11675948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Sep 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.