System and method for performing small channel count convolutions in energy-efficient input operand stationary accelerator
US11675998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2019 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Aug 22, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein includes a system, a method, and a device for receiving input data to generate a plurality of outputs for a layer of a neural network. The plurality of outputs are arranged in a first array. Dimensions of the first array may be compared with dimensions of a processing unit (PE) array including a plurality of PEs. According to a result of the comparing, the first array is partitioned into subarrays by the processor. Each of the subarrays has dimensions less than or equal to the dimensions of the PE array. A first group of PEs in the PE array is assigned to a first one of the subarrays. A corresponding output of the plurality of outputs is generated using a portion of the input data by each PE of the first group of PEs assigned to the first one of the subarrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.