Memory sub-system with a bus to transmit data for a machine learning operation and another bus to transmit host data
US11676010B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Oct 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/049
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory component to store host data from a host system and to store a machine learning model and input data. A controller includes an in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and provide the additional host data to the memory component. An additional bus can receive machine learning data from the host system and provide the machine learning data to the in-memory logic that is to perform the machine learning operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.