Semiconductor device structure and methods of forming the same
US11676862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Jun 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.