Selective dual silicide formation

US11676868B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Wei-Yip Loh · Hsinchu, TW
• Yan-Ming Tsai · Gongguan, TW
• Yi-Ning Tai · Hsinchu, TW
• Raghunath PUTIKAM · Hsinchu, TW
• Hung-Yi Huang · Jinshanmian, TW
• Hung-Hsu Chen · Tainan, TW
• Chih-Wei Chang · Nan'ao, TW

Key dates

• Filing date: Aug 19, 2021
• Grant date: Jun 13, 2023
• Expiry date: Aug 19, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/64

Abstract

Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.