Inventor · Hsinchu, TW

Wei-Yip Loh

39Patents
5h-index
56Co-inventors
68Inventor score

Filing activity: Mar 3, 2005 → Jan 2, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US8362494B2 Electro-optic device with novel insulating structure and a method for manufacturing the same Physics 24 Active
US7294890B2 Fully salicided (FUSA) MOSFET structure Electricity 16 Expired
US8436422B2 Tunneling field-effect transistor with direct tunneling for enhanced tunneling current Electricity 11 Active
US9029218B2 Tunneling field-effect transistor with direct tunneling for enhanced tunneling current Electricity 6 Active
US8421165B2 Apparatus, system, and method for tunneling MOSFETs using self-aligned heterostructure source and isolated drain Electricity 5 Active
US7682914B2 Fully salicided (FUCA) MOSFET structure Electricity 5 Active
US11348839B2 Method of manufacturing semiconductor devices with multiple silicide regions Electricity 4 Active
US10535748B2 Method of forming a contact with a silicide region Electricity 3 Active
US7439165B2 Method of fabricating tensile strained layers and compressive strain layers for a CMOS device Electricity 3 Active
US10504834B2 Contact structure and the method of forming the same Electricity 2 Active
US8178939B2 Interfacial barrier for work function modification of high performance CMOS devices Electricity 2 Active
US11373905B2 Semiconductor device pre-cleaning Electricity 2 Active
US10755917B2 Treatment for adhesion improvement Electricity 2 Active
US11031286B2 Conductive feature formation and structure Electricity 1 Active
US11232947B1 Ammonium fluoride pre-clean protection Electricity 1 Active
US11195791B2 Method for forming semiconductor contact structure Electricity 0 Active
US11335774B2 Contact structure for semiconductor device and method Electricity 0 Active
US11411094B2 Contact with a silicide region Electricity 0 Active
US12166078B2 Contact structure for semiconductor device and method Electricity 0 Active
US11915976B2 Semiconductor device pre-cleaning Electricity 0 Active
US11810826B2 Semiconductor devices with stacked silicide regions Electricity 0 Active
US12328890B2 Contact with a silicide region Electricity 0 Active
US12218012B2 Method of manufacturing semiconductor devices with multiple silicide regions Electricity 0 Active
US11676868B2 Selective dual silicide formation Electricity 0 Active
US12300542B2 Semiconductor device pre-cleaning Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.