Method to enable 30 microns pitch EMIB or below

US11676891B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Hongxia Feng · Chandler, US
• Dingying Xu · Chandler, US
• Sheng Li · Santa Clara, US
• Matthew Tingey · Hillsboro, US
• Meizi Jiao · Chandler, US
• Chung Kwang Christopher Tan · Chandler, US

Key dates

• Filing date: Jun 30, 2021
• Grant date: Jun 13, 2023
• Expiry date: Dec 16, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.