Metrology targets for high topography semiconductor stacks
US11676909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2020 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Feb 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metrology target for use in measuring misregistration between layers of a semiconductor device including a first target structure placed on a first layer of a semiconductor device, the first target structure including a first plurality of unitary elements respectively located in at least four regions of the first target structure, the first plurality of elements being rotationally symmetric with respect to a first center of symmetry and at least a second target structure placed on at least a second layer of the semiconductor device, the second target structure including a second plurality of elements respectively located in at least four regions of the second target structure, the second plurality of elements being rotationally symmetric with respect to a second center of symmetry, the second center of symmetry being designed to be axially aligned with the first center of symmetry and corresponding ones of the second plurality of elements being located adjacent corresponding ones of the first plurality of elements in the at least four regions in a non-surrounding arrangement, when the first and second layers are placed one on top of another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.