Integrated device comprising interconnect structures having an inner interconnect, a dielectric layer and a conductive layer

US11676922B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Li-Sheng Weng · San Diego, US
• Yue Li · San Diego, US
• Yangyang SUN · Qingdao, CN

Key dates

• Filing date: Oct 28, 2019
• Grant date: Jun 13, 2023
• Expiry date: Nov 8, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.