Semiconductor packages
US11676923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2020 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Jul 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.