Apparatuses, methods, and systems for access synchronization in a shared memory
US11681529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2021 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Sep 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.