Computational array microprocessor system using non-consecutive data formatting
US11681649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2021 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Oct 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together to the computational array as a group of values to be processed in parallel. The hardware data formatter is configured to gather the group of values, wherein the group of values includes a first subset of values located consecutively in memory and a second subset of values located consecutively in memory. The first subset of values is not required to be located consecutively in the memory from the second subset of values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.