Patent · US Active

Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs

US11681846B1 · kind B1 · utility

0Cited by

2References

4Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Xiaojian Yang · Sunnyvale, US
Frederic Revenu · San Carlos, US
Dinesh D. Gaitonde · Fremont, US
Amit Gupta · Redmond, US

Key dates

Filing date	Jan 12, 2021
Grant date	Jun 20, 2023
Priority date	—
Expiry date	Jan 12, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/347
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.