Memory component with a bus to transmit data for a machine learning operation and another bus to transmit host data
US11681909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Jul 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/049
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells can include a memory region to store a machine learning model and input data and another memory region to store host data from a host system. An in-memory logic can be coupled to the plurality of memory cells and can perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and can provide the additional host data to the memory component for the other memory region of the plurality of memory cells. An additional bus can receive machine learning data from the host system and can provide the machine learning data to the memory component for the in-memory logic that is to perform the machine learning operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.