Multi-tier memory architecture
US11682432B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2021 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Jun 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.