Patent · US Active

Method for forming transistor structures

US11682591B2 · kind B2 · utility

0Cited by

3References

10Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Boon Teik Chan · Wilsele, BE
Juergen Boemmels · Heverlee, BE
Basoene Briggs · Heverlee, BE

Key dates

Filing date	Aug 24, 2021
Grant date	Jun 20, 2023
Priority date	—
Expiry date	Aug 24, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/038
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.