Connector for implementing multi-faceted interconnection
US11682621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2021 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Sep 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A connector for implementing multi-faceted interconnection according to an embodiment of the present disclosure includes a first dielectric layer between a first circuit layer and a second circuit layer, a first copper pillar layer connecting the first circuit layer and the second circuit layer in the first dielectric layer, a second dielectric layer on the first circuit layer, a third circuit layer on the second dielectric layer, and a vertical second copper pillar layer connected to the third circuit layer, wherein an opening is formed in the second dielectric layer to expose the first circuit layer, and the second copper pillar layer exposes side faces facing side end faces of the first dielectric layer and the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.