Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
US11687254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2019 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jan 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.