Processor overriding of a false load-hit-store detection
US11687337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Aug 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.