Brian Chen
16Patents
10h-index
10Co-inventors
69Inventor score
Filing activity: Mar 18, 1997 → Aug 20, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6272660A | Screening for errors in data transmission systems | Electricity | 60 | Expired |
| US6347122B1 | Optimal complement punctured convolutional codes for use in digital audio broadcasting and other applications | Electricity | 41 | Expired |
| US6105158A | Screening for undetected errors in data transmission systems | Electricity | 32 | Expired |
| US6445750B1 | Technique for communicating digitally modulated signals over an amplitude-modulation frequency band | Electricity | 23 | Expired |
| US6215815A | Band insertion and precancellation technique for simultaneous communications of analog frequency-modulated and digitally modulated signals | Electricity | 22 | Expired |
| US6161210A | List Viterbi algorithms for tailbiting convolutional codes | Electricity | 21 | Expired |
| US6075813A | Band insertion and precancellation technique for simultaneous communication of analog frequency modulated and digitally modulated signals | Electricity | 14 | Expired |
| US6108386A | List Viterbi algorithms for continuous data transmission | Electricity | 13 | Expired |
| US6768778B1 | Optimal complementary punctured convolutional codes | Electricity | 12 | Expired |
| US6199186A | Screening for undetected errors in data transmission systems | Electricity | 10 | Expired |
| US11263151B2 | Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations | Physics | 0 | Active |
| US11321088B2 | Tracking load and store instructions and addresses in an out-of-order processor | Physics | 0 | Active |
| US11243773B1 | Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges | Physics | 0 | Active |
| US11687337B2 | Processor overriding of a false load-hit-store detection | Physics | 0 | Active |
| US11379241B2 | Handling oversize store to load forwarding in a processor | Physics | 0 | Active |
| US11314510B2 | Tracking load and store instructions and addresses in an out-of-order processor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.