Shared error correction code (ECC) circuitry
US11687407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Aug 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described apparatuses and methods provide error correction code (ECC) circuitry that is shared between two or more memory banks of a memory, such as a low-power dynamic random-access memory (DRAM). A memory device may include one or more dies, and a die can have multiple memory banks. The ECC circuitry can service at least two memory banks by producing ECC values based on respective data stored in the two memory banks. By sharing the ECC circuitry, instead of including a per-bank ECC engine, a total die area allocated to ECC functionality can be reduced. Thus, the ECC circuitry can be elevated from a one-bit ECC algorithm to a multibit ECC algorithm, which may increase data reliability. In some cases, memory architecture may operate in environments in which a masked-write command or an internal read-modify-write operation is precluded, including with shared ECC circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.