Priority-based cache-line fitting in compressed memory systems of processor-based systems
US11687461B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Feb 13, 2042 |
Classification
- Technology area (CPC —)General
Abstract
A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.