Gurvinder Singh Chhabra
20Patents
4h-index
47Co-inventors
59Inventor score
Filing activity: Sep 27, 2007 → Jan 10, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8898448B2 | Hardware acceleration for WWAN technologies | Emerging Cross-Sectional Technologies | 9 | Active |
| US9615401B2 | Methods and apparatus for updating a device configuration | Electricity | 5 | Active |
| US9652152B2 | Efficient decompression locality system for demand paging | Physics | 4 | Active |
| US9876613B2 | Transport protocol communications reduction | Electricity | 4 | Active |
| US8954045B2 | Method and apparatus for managing resources at a wireless device | Electricity | 4 | Active |
| US10169246B2 | Reducing metadata size in compressed memory systems of processor-based systems | Physics | 4 | Active |
| US10198362B2 | Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems | Physics | 3 | Active |
| US9823854B2 | Priority-based access of compressed memory lines in memory in a processor-based system | Physics | 3 | Active |
| US11782762B2 | Stack management | Physics | 1 | Active |
| US9379887B2 | Efficient cryptographic key stream generation using optimized S-box configurations | Electricity | 1 | Active |
| US9319878B2 | Streaming alignment of key stream to unaligned data stream | Emerging Cross-Sectional Technologies | 1 | Active |
| US11416236B2 | Over-the-air (OTA) updating of partially compressed firmware | Electricity | 1 | Active |
| US10061698B2 | Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur | Emerging Cross-Sectional Technologies | 0 | Active |
| US10482021B2 | Priority-based storage and access of compressed memory lines in memory in a processor-based system | Physics | 0 | Active |
| US10678705B2 | External paging and swapping for dynamic modules | Physics | 0 | Active |
| US11687461B1 | Priority-based cache-line fitting in compressed memory systems of processor-based systems | General | 0 | Revoked |
| US11868244B2 | Priority-based cache-line fitting in compressed memory systems of processor-based systems | Physics | 0 | Active |
| US10372459B2 | Training and utilization of neural branch predictor | Physics | 0 | Active |
| US11829292B1 | Priority-based cache-line fitting in compressed memory systems of processor-based systems | Physics | 0 | Active |
| US9600420B2 | Reducing decompression time without impacting compression ratio | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.