Nonvolatile memory device with capability of determining degradation of data erase characteristics
US11688478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2022 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Mar 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.