Semiconductor package and method for fabricating a semiconductor package

US11688670B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Ralf Otremba · Kaufbeuren, DE
• Paul Frank · Villach, AT
• Alexander Heinrich · Bad Abbach, DE
• Alexandra Ludsteck-Pechloff · Unterhaching, DE
• Daniel Pedone · Munich, DE

Key dates

• Filing date: Oct 26, 2020
• Grant date: Jun 27, 2023
• Expiry date: Feb 13, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3841
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.