Integrated circuit structure with source/drain spacers
US11688768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The device includes a semiconductor substrate and a stack of channel layers on the semiconductor substrate. A top surface of a topmost channel layer extends along a first height relative to the substrate surface. A bottom surface of a bottommost channel layer extends along a second height relative to the substrate surface. The device further includes a gate structure that engages with the stack of channel layers and extending along a first direction. Additionally, the device includes a source/drain feature on first sidewall surfaces of the stack of channel layers and on the substrate, where the first sidewall surfaces extends in parallel to the first direction. Moreover, the source/drain feature has a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.