Transistor level interconnection methodologies utilizing 3D interconnects
US11688776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Mar 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.