Adeia Semiconductor Inc.
19Patents
19Active
19Granted
62Portfolio score
Filing activity: Sep 7, 2018 → Dec 28, 2023
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11515291B2 | Integrated voltage regulator and passive components | Electricity | 30 | Active |
| US11916076B2 | Device disaggregation for improved performance | Electricity | 12 | Active |
| US11557516B2 | 3D chip with shared clock distribution network | Electricity | 3 | Active |
| US11688776B2 | Transistor level interconnection methodologies utilizing 3D interconnects | Electricity | 1 | Active |
| US11914148B2 | Stacked optical waveguides | Physics | 1 | Active |
| US11894345B2 | Integrated voltage regulator and passive components | Electricity | 1 | Active |
| US11790219B2 | Three dimensional circuit implementing machine trained network | Electricity | 1 | Active |
| US11881454B2 | Stacked IC structure with orthogonal interconnect layers | Electricity | 1 | Active |
| US12142528B2 | 3D chip with shared clock distribution network | Electricity | 1 | Active |
| US12293993B2 | 3D chip sharing data bus | Electricity | 0 | Active |
| US12035529B2 | 3D NAND—high aspect ratio strings and channels | Electricity | 0 | Active |
| US12401010B2 | 3D processor having stacked integrated circuit die | Electricity | 0 | Active |
| US12248869B2 | Three dimensional circuit implementing machine trained network | Electricity | 0 | Active |
| US12278215B2 | Integrated voltage regulator and passive components | Electricity | 0 | Active |
| US12362182B2 | Direct-bonded native interconnects and active base die | Electricity | 0 | Active |
| US12074092B2 | Hard IP blocks with physically bidirectional passageways | Emerging Cross-Sectional Technologies | 0 | Active |
| US11862604B2 | Systems and methods for releveled bump planes for chiplets | Electricity | 0 | Active |
| US12218059B2 | Stacked IC structure with orthogonal interconnect layers | Electricity | 0 | Active |
| US12272730B2 | Transistor level interconnection methodologies utilizing 3D interconnects | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.