Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors
US11689213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jun 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.