Method and system for error correction in memory devices using irregular error correction code components
US11689219B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Aug 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.