Memory architecture at back-end-of-line
US11690212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Oct 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe techniques for a semiconductor device including a substrate. A first set of memory cells and a first selector are formed within a first group of metal layers and inter-level dielectric (ILD) layers above the substrate. A second set of memory cells and a second selector are formed within a second group of metal layers and ILD layers above the first group of metal layers and ILD layers. The first selector is coupled to the first set of memory cells to select one or more memory cells of the first set of memory cells based on a first control signal. In addition, the second selector is coupled to the second set of memory cells to select one or more memory cells of the second set of memory cells based on a second control signal. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.