Fatih Hamzaoglu
41Patents
6h-index
72Co-inventors
72Inventor score
Filing activity: Sep 29, 2000 → Oct 17, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6519176B1 | Dual threshold SRAM cell for single-ended sensing | Physics | 30 | Expired |
| US7403426B2 | Memory with dynamically adjustable supply | Physics | 27 | Expired |
| US7079426B2 | Dynamic multi-Vcc scheme for SRAM cell stability control | Physics | 26 | Expired |
| US7177176B2 | Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength | Physics | 14 | Expired |
| US8451670B2 | Adaptive and dynamic stability enhancement for memories | Physics | 12 | Active |
| US6608786B2 | Apparatus and method for a memory storage cell leakage cancellation scheme | Physics | 11 | Expired |
| US10515697B1 | Apparatuses and methods to control operations performed on resistive memory cells | Physics | 6 | Active |
| US6801465B2 | Apparatus and method for a memory storage cell leakage cancellation scheme | Physics | 5 | Expired |
| US9478273B2 | Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory | Physics | 5 | Active |
| US9111600B2 | Memory cell with improved write margin | Physics | 5 | Active |
| US9455011B2 | Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current | Physics | 5 | Active |
| US9286976B2 | Apparatuses and methods for detecting write completion for resistive memory | Physics | 5 | Active |
| US8406073B1 | Hierarchical DRAM sensing | Physics | 4 | Active |
| US7657767B2 | Cache leakage shut-off mechanism | Emerging Cross-Sectional Technologies | 4 | Active |
| US9865322B2 | Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory | Physics | 3 | Active |
| US11462541B2 | Memory cells based on vertical thin-film transistors | Electricity | 2 | Active |
| US9978447B2 | Memory cell with improved write margin | Physics | 1 | Active |
| US6351156B1 | Noise reduction circuit | Physics | 1 | Expired |
| US9666268B2 | Apparatus for adjusting supply level to improve write margin of a memory cell | Physics | 1 | Active |
| US9805790B2 | Memory cell with retention using resistive memory | Physics | 1 | Active |
| US8456946B2 | NAND logic word line selection | Physics | 1 | Active |
| US9330747B2 | Non-volatile latch using spin-transfer torque memory device | Physics | 1 | Active |
| US10068628B2 | Apparatus for low power write and read operations for resistive memory | Physics | 1 | Active |
| US9922691B2 | Resistive memory write circuitry with bit line drive strength based on storage cell line resistance | Physics | 1 | Active |
| US9281043B1 | Resistive memory write circuitry with bit line drive strength based on storage cell line resistance | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.