Three-dimensional memory device having parallel trench type capacitor
US11690233B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jul 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A 3D memory device may include a logic device layer on a substrate and a memory device layer stacked on the logic device layer. The logic device layer may include logic devices disposed on the substrate. The memory device layer may include a word line stack disposed in an extension area, staircase patterns disposed in the word line stack, a dielectric layer stack in a peripheral area, and capacitors inlayed in the dielectric layer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.