Patent · US Active

Scan chain for memory with reduced power consumption

US11693056B1 · kind B1 · utility

1Cited by

1References

15Claims

0Family size

Assignee

Ceremorphic, Inc. · US

Inventors

Robert Francis Wiser · San Francisco, US
Shakti Singh · Barwala, IN
Neelam Surana · Redlapalli, IN

Key dates

Filing date	Dec 22, 2021
Grant date	Jul 4, 2023
Priority date	—
Expiry date	Dec 22, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318583
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.