Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm
US11693662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2020 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Jul 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.