Reformatting scan patterns in presence of hold type pipelines
US11694010B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 3, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Dec 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.