Memory sub-system with internal logic to perform a machine learning operation
US11694076B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Oct 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/049
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory component can include memory cells where a first region of the memory cells is to store a machine learning model and a second region of the memory cells is to store input data and output data of a machine learning operation. A controller can be coupled to the memory component with one more internal buses to perform the machine learning operation by applying the machine learning model to the input data to generate the output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.