Barrier free interface between beol interconnects
US11694926B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Sep 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.